SwCC: Software-Programmable and Per-Packet Congestion Control in RDMA Engine

on YouTube ↗19m

" summary

SwCC embeds on-NIC RISC-V cores and a QP-aware memory subsystem on a Xilinx U280 FPGA to run per-packet congestion control in software while matching hardware NIC performance. It reports 3.1 µs control loop RTT and needs 512B to reach 100 Gbps like ConnectX-5, reduces CC handling CPU cycles by 91% versus BlueField-like DPU baselines, implements diverse CCAs in under 200 lines of C, and estimates a 2.5 GHz core suffices for 800 Gbps with its design.

AI-written summary · about

" chapters (16)

1. 0:00SWCC and congestion control intro
2. 1:24Control loop delay challenges
3. 2:53Limitations of existing CC
4. 5:20Hardware offloading trade-offs
5. 7:35SWCC design goals
6. 8:41TSX multicore design
7. 10:09QP memory optimization
8. 11:13Extensible CC handle
9. 12:20User-defined QP context
10. 13:29CCA deployment APIs
11. 14:18Experimental validation
12. 15:47Control loop delay results
13. 16:08CC controller intervals
14. 16:30Diverse CCAs support
15. 17:14Processor frequency needs
16. 18:02Summary and conclusion

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