White-Boxing RDMA with Packet-Granular Software Control
summary
Claims software control of RDMA transport at packet granularity while preserving line‑rate data path performance, implemented on Nvidia BlueField-3 DPA and using its RISC‑V embedded cores. Key mechanisms: repurposing hardware rate assignment into a “decorate rate” control knob, hardware+software event coraling to batch packet events (handles 100 Gbps, ~120 ns packet intervals), run‑to‑completion processing and cache optimizations. Demonstrates Multi‑Tenant Fair Scheduler, user‑defined congestion and receiver‑driven flow control, multi‑path routing, plus GPU‑Direct and NVMe‑oF support with no app changes.
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chapters (14)
- 0:00White-boxing RDMA intro
- 1:21Customizing RDMA transport
- 3:29Programmable NICs for control
- 4:33White-boxing RDMA challenges
- 5:16SCR framework overview
- 6:44Decor rate control model
- 7:24Packet-level granularity handling
- 9:54Scalability with granularity invariance
- 11:40BlueField-3 with DPA implementation
- 12:44Fair QPuler flexibility demo
- 14:49Fairness and utilization results
- 15:32Fine-tuning with SCR algorithms
- 16:38Beyond QPuler use cases
- 17:00Summary and future
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