Scaling IP Lookup to Large Databases using the CRAM Lens
summary
A formal CRAM lens evaluation shows concrete mappings and tradeoffs for RMT/DRMT chips: a DAG-based CRA model plus eight optimization idioms predicts memory and step counts, and P4 mappings expose hardware limits (Tofino‑2 needs 16–30 stages versus CRAM’s 2–14 predicted steps). New schemes—RESAIL and hybrid tries—use small TCAM plus SRAM to scale IPv4 to 2.25M IPv4 prefixes (vs ~250k for pure TCAM) and IPv6 to ~390k (3.2× pure TCAM).
AI-written summary · about
chapters (14)
- 0:00CRAM model introduction
- 1:19CRAM overview
- 3:03RMT DRMT memory background
- 4:49CRAM motivations and limits
- 5:52CRAM definition and workflow
- 7:16CRAM optimization idioms
- 8:41Why IP lookup scaling matters
- 9:23CRAM applied to SALE algorithm
- 10:47DXR adaptation for IPv6
- 11:52Hybrid multi-bit tries
- 12:35Experimental results and P4
- 13:58CRAM accuracy and scalability
- 14:39IPv4 IPv6 performance gains
- 15:00Future directions and conclusion
related talks
18mFileMR: Rethinking RDMA Networking for Scalable Persistent Memory
17mDRack: A CXL-Disaggregated Rack Architecture to Boost Inter-Rack Communication
18mMORP4: A Dynamic Network Telescope
16mGRO Library Enhancements
17mSRNIC: A Scalable Architecture for RDMA NICs
17mPlanB: Efficient Software IPv6 Lookup with Linearized B+-Tree
18mTiara: A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-4
14mMultitenancy for Fast and Programmable Networks in the Cloud
