Themis: Scheduling-Aware Buffer Management for HBM-Based Hybrid Buffers

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" summary

Themis places packets by P4 rank, keeps rank-based admission to favor soon-to-depart packets in SRAM, and uses batch swap in/out to write and read contiguous HBM blocks organized by scheduling order. Evaluation uses NS-3 simulations and hardware prototypes on FPGA and ASIC. Results show HBM throughput up to 790 Gbps (baseline ~650 Gbps), link utilization near 100% versus 50–70%, packet loss reduced 18–90%, ~2× improvement in on-chip dequeue hit rate and 99th‑percentile FCT, and hardware cost ~134 LUTs, 88 FFs, ~0.2 mm².

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" chapters (15)

1. 0:00Introduction
2. 0:41HBM challenges
3. 2:06Optimal HBM bandwidth rules
4. 2:48Hybrid buffer limits
5. 3:51HBM inefficiency example
6. 6:22Scheduling-aware buffer idea
7. 7:25Rank-based admission & batching
8. 9:35Swap primitives
9. 11:00Example with Themis
10. 13:30Themis benefits & design
11. 13:51Evaluation method
12. 14:55Throughput & link utilization
13. 15:16Packet loss & hit rate
14. 15:37Flow time & hardware cost
15. 16:40Conclusion & Q&A

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