Faster Software Packet Processing on FPGA NICs with eBPF Program Warping
summary
Program warping statically analyzes unmodified Linux eBPF/XDP bytecode, identifies initial parse-and-key-construction sequences, and replaces them with a runtime-programmable FPGA pipeline (the warp engine) that emits match-action rules and a restore-context operation to resume execution in the hXDP executor. A prototype on a 100Gbps FPGA NIC runs at 250MHz, uses <15% FPGA resources, evaluates 6 real-world programs including Katran and Suricata, and improves hXDP throughput typically 1.2–3× and up to 18× while preserving functional equivalence.
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chapters (20)
- 0:00Intro
- 0:32Software Packet Processing?
- 1:01Scaling Software Packet Processing
- 2:09Anatomy of a Network Interface Card
- 3:05How to program the network data plane?
- 4:14How to run eBPF on the NIC?
- 8:01Anatomy of an eBPF program
- 8:48hXDP: run program on specialized VLIW processor
- 9:26Common operations for eBPF programs
- 11:06Simplified executor for common operations
- 12:22Program Warping
- 13:11Packet processing dynamics
- 13:38The Warp Optimizer
- 17:51The Warp Engine
- 20:58The overall picture
- 21:54Does it work?
- 22:36Software Emulator and Reference Use Cases
- 23:46Functional Equivalence
- 24:19Number of "warped" instructions
- 24:56Hardware resources
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