FpgaNIC: An FPGA-based Versatile 100Gb SmartNIC for GPUs
summary
FpgaNIC is an FPGA SmartNIC that enables GPU virtual address P2P so GPUs talk to NICs over PCIe without CPU copies, implements a reliable 100Gb hardware transport, and leaves <20% FPGA resources free for custom datapath accelerators. Experiments on eight servers with Xilinx U280/U50 FPGAs and NVIDIA A100 GPUs show direct data-plane and control-plane offload cuts PCIe command serialization (three CPU commands reduced to GPU-driven flow), matches CPU-memory throughput to GPU memory, stabilizes latency, and gives clear speedups for small (<1 MB) and large (>2 MB) transfers. Source on GitHub.
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chapters (14)
- 0:00Intro
- 0:34Outline
- 1:09Why GPU-centric SmartNIC?
- 2:03Why FPGA-based SmartNIC?
- 4:10FpgaNIC: GPU Communication Stack
- 4:26Data Plane Offloading vs. Without Offloading
- 5:48Control Plane Offloading vs. Without Offloading
- 7:53FpgaNIC: Hardware Network Transport
- 8:49FpgaNIC: On-NIC Computing
- 11:52Experimental Setup
- 12:22Goal of Experiment
- 13:01FpgaNIC: Functionality
- 14:35FpgaNIC: GPU-centric Networking (Direct Model)
- 17:45FpgaNIC: HyperLogLog (On-path Model)
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