RISC-V Summit North America 2025
2025-10-22..2025-10-23
Santa Clara, United States
[RISC-V Summit North America 2023, RISC-V Summit North America 2024, RISC-V Summit North America 2025]
| title | author | length |
|---|---|---|
| Networking-Native RISC-V Processor for Datacenter | Mark Throndson | 18m |
A RISC‑V I8500 core is built for line‑rate packet work: RVB23 with SV39/SV48, big‑endian execution, an in‑order three‑issue pipeline and 4‑way SMT that lets… | ||
| Accelerating Software Development for High Performance Chiplet... | R. Parnmukh, L. Yen, L. Lapides | 12m |
Describes building Synopsys Virtualizer VDKs that model a Tenstorrent chiplet, memory and PCIe IO, using TLM SystemC components and a licensed Escalon… | ||
| Utilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling | Dennis Griffith | 21m |
Lauterbach demonstrates use of the E-Trace and N-Trace standards to record without stopping CPUs, funnel multiple streams through on‑chip encoders and a sync… | ||
| Understanding the RISC-V Extensions for AI | John Simpson | 20m |
RISC‑V proposals target matrix work by adding either new instructions inside vectors or new matrix state; batch.product fasttrack does eight dot‑products in… | ||
| Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC... | R. Fuhler | 15m |
Packed-SIMD P extension work targets scalar DSP patterns and ships preliminary mnemonics, opcodes, SAIL models, draft docs and POC LLVM/binutils and upstream… | ||
| Enabling Intelligent Media Playback on RISC-V - Running VLC With Whisper STT and Qwen T2... | Y. Liang | 17m |
Runs VLC on an ESWIN EIC7702 SoC with a 40 TOPS NPU, integrating Whisper STT and Qwen T2T by porting a 7B model to the MPU and adding GGML tiny integration… | ||
| AI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at Scale | Z. Paz, M. Evans | 18m |
ProteanTecs IP embeds tiny on‑chip margin agents under real logic paths and Andes AX45MPV supports up to 2048-bit vectors; a prototype 5 nm chip runs about 500… | ||
| Next-Generation Edge AI with RISC-V Vector Cores for Vision Applications | Florian Zaruba | 17m |
RISC‑V vector cores are integrated as two programmable vector engines of 2x8 CVA6V cores with 2MB scratchpad each that move 2D image data locally to avoid PCIe… | ||
| RISC-V is Ready for Powering the Era of Intelligent General Computing | Charlie Su | 17m |
Claims concrete hardware and software wins: Andes offers AX46MPV with up to 1024-bit vector and memory-path optimizations that boost vector bandwidth ~40% and… | ||
| ChipIN Centre: Accelerating India’s Journey in RISC-V | Venkata Reddy K, Aneesh Raveendran | 16m |
ChipIN Centre provides centralized access to Synopsys, Cadence, Siemens/KeySight and other industry EDA suites, FPGA prototyping (Xilinx/AMD boards), Param… | ||
| Automated Certification and Benchmarking for RISC-V Architectures | Enrique Pallares | 16m |
Claims a reproducible benchmarking pipeline that cuts toolchain setup from two–three days to about half a day (≈3x faster) and automates ~85% of benchmarking… | ||
| The Big-endian RISC-V Linux Adventure | Roan Richmond, Lawrence Hunter | 18m |
Runtime-configurable big-endian RISC‑V is implemented end-to-end: CSRs control endian bits and the project modifies Linux kernel, QEMU, OpenSBI, CVA6 and… | ||
| Unlocking the Potential of RISC-V With TrusteD-V: A RISC-V Rust Software Ecosystem | Y. Singh M | 15m |
TrusteD‑V is a Rust‑first RISC‑V SDK that generates a chip‑specific middleware stack from bootloader to OS, plus secure bootloaders, drivers, toolchains and a… | ||
| How NOT To Program an Out-of-order Vector Processor | Dongjie Xie, Chip Kerchner | 19m |
Benchmarks on two RVV-capable designs compare handcrafted and compiler-vectorized code and show concrete wins and failures: using strip mining usually improves… | ||
| Boosting Video Codec With RISC-V Vector Extension | Jing Qiu, Jiayan Qian | 20m |
Hardware and software co-design uses ZvZip for in-register reordering (reducing instruction count by about one third), Zvabd for SAD/SATD (about 20% per-op… | ||
| Nuclei System Technology Releases UX1030H with Full Support for RVA23 | Dr. Peng Chen | 19m |
Nuclei releases UX1030H claiming full RVA23 compliance with integrated IOMMU, Advanced Interrupt Architecture and an interrupt distribution unit plus cache… | ||
| Welcome & Opening Remarks | Andrea Gallo | 21m |
Announcements include a market forecast of 33.7% RISC‑V penetration by 2031, ratified RVA23 profile now endorsed by Android and supported in Ubuntu 25.10 and… | ||
| Keynote: From Hardware Innovation to a Thriving RISC-V Ecosystem | Jing Yang | 15m |
Alibaba reports concrete milestones: C910 open sourced with 80+ papers citing it and 20+ commercial IPs built on it, a TH1520 board family running Linux/AOSP… | ||
| Keynote: Paving the Road to Datacenter-Scale RISC-V | Martin Dixon | 16m |
Google describes a playbook: port 30,000+ packages to multiarch using CI/CD and automation, feed ~40,000 real code edits into Gemini to categorize fixes, and… | ||
| Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulat... | W. Han, A. Sutton | 18m |
Demonstrates a Synopsys workflow that runs XiangShan on FPGA/emulation (Zebu/Haps) with Sting/SRM generating many self-checking ELF files using a reference… | ||
| RISC-V Customization After a Tape-out | Zdenek Prikryl, Gareth Baron | 18m |
Demonstration shows post-tape-out ISA extension by mapping a new RISC-V custom instruction into an on-chip e-FPGA, using Codasip L110 plus Studio (kodal → RTL… | ||
| Verifying Out-Of-Order RISC-V Vector Extension With Open Source Tools | S. Panandikar, A. Kumar | 16m |
An open-source verification stack verifies an out-of-order RVV 1.0 implementation (plus BF16, bitmanip, crypto and dot product extensions) by combining Riescue… | ||
| Automating Design Space Exploration Using Advanced Simulation Technologies | K. Lingaard, S. Grove | 14m |
A spec-driven workflow combines an Instruction Set Simulator, trace-driven C++ microarchitectural models and Atlas Explorer to run early design space… | ||
| Enabling RISC-V Success: From Design to Deployment | Geir Eide | 17m |
Siemens EDA shows a concrete end-to-end RISC‑V flow: C++ to synthesizable RTL via high‑level synthesis for accelerators, exhaustive formal verification of… | ||
| GPON Solution Demonstrating VOLTHA Stack on RISC-V | Partha Mitra | 16m |
A working GPON OLT runs the open-source VOLTHA stack ported to RISC‑V on a Microchip PolarFire SoC, with the OLT MAC in the FPGA and control/DBA on the RISC‑V… | ||
| Efficient RISC-V Processor Customization: Minimizing Verification Efforts | Zdenek Prikryl | 17m |
Codasip ships a Bounded Customization methodology that confines extensions to a sandbox and enforces rules via a YAML config so the rest of the core never… | ||
| RISC-V System-level Certification from Verification Foundations | Adnan Hamid | 25m |
Covers concrete system-level tests and a toolchain that synthesizes C+ASM tests and TBX testbenches from graph models, exercising atomics, cache coherency, AIA… | ||
| Keynote: RISC-V Outperforming Expectations | Richard Wawrzyniak | 17m |
New 2025 forecast raises RISC‑V unit shipments sharply after updated China data, projecting 35 billion units by 2031 with about a 31.7% CAGR; market revenues… | ||
| Keynote: Securing the Final Frontier: RISC-V® in Space and Critical Infrastructure | Ted Speers | 15m |
Microchip claims RISC-V is production-ready in space: it ships a Polar Fire SOC (announced 2018, first silicon fabbed), centers HPSC on a SiFive X288 8-core… | ||
| A RISCy Approach to Microprocessor Technology | David Patterson | 14m |
Berkeley designs a simple RISC ISA in 1980, teaches it through three courses, and sends student layouts to fabrication using in-house CAD, Unix tools and the… | ||
| Keynote: Lightning Round | Andrew Moore | 30m |
Seventeen companies give two- or one-minute updates claiming concrete outcomes: AANA touts RVV23 out-of-order cores and SMT data movers for AI/auto; Axelera… | ||
| Keynote Panel: Linux and RISC-V: Principles for a Winning Partnership | Barna Ibrahim, Steve Wanless, Gordan Markuš, Darren Davis | 30m |
Multiple distributions now target RISC‑V with concrete work: an upstream kernel bump 6.5 → 6.12, a supported profile RVA23, and public builds via… | ||
| Demo: XuanTie High-Performance Processors with Continuous Innovation and Iteration | Ren Guo | 21m |
C930 is a ground-up microarchitecture claiming six decode and 16 stage pipeline with aggressive front end and full MMU features including nested translation… | ||
| Demo: LED Cube Using RISC-V®-Based PolarFire® SoC FPGA | Krishnakumar R | 20m |
Demo reproduces Adafruit’s 6-panel hub75 cube on a BeagleV®-Fire module with a PolarFire SoC FPGA, driving six 64×64 panels (≈24,000 RGB pixels ≈75,000 LEDs)… | ||
| Demo: RISC-V AIA Expanding Interrupts: Applications, Implementation and Verification | Adnan Hamid | 17m |
Demonstrates a test-suite synthesis flow that configures the RISC-V AIA (per-hart MSIC per hart and system APLIC), generates C with inline asm plus a TBX… | ||
| Demo: Neural Network Acceleration on Metis, Powered by RISC-V | Florian Zaruba, Victor Labian Carro | 07m |
Metis is a quad‑AI‑core edge inference accelerator with a central RISC-V controller and a digital array for digital in-memory computing that performs… | ||
| Tenstorrent: Extending the RISC-V Open Source Ecosystem | Darshak Koshiya | 08m |
Tenstorrent is releasing concrete artifacts: an open source Ocelot vector core (Boom with vector extensions), a recently published DFD instruction trace IP and… | ||
| Demo: Akeana: Highest Performance, Customized Cores, Multi-core/Multi-thread Clusters- | Graham Wilson | 12m |
Soft IP portfolio includes RV32 100-series, RV64 1000-series, and high-end AANA 5000 cores with up to 4 threads and vector extensions reaching 4K vector… | ||
| Demo: Insightful Debugging & Optimization: System-wide Functional Monitoring with Tessent... | F. Tan | 10m |
Claims a scalable end-to-end system for visibility: silicon‑proven, configurable embedded monitors plus a host SDK and a generator that emits a… | ||
| Keynote: RISC-V State of the Union | Krste Asanovic | 20m |
RISC‑V claims clear momentum: entrenched in embedded, adopted as the default for new AI accelerators, and gaining traction in automotive and server spaces with… | ||
| Keynote: Designing Processors in the Cloud: How Advanced Emulation and AWS Cloud Infrast... | J. Dahan | 16m |
Cloud workflow shows FPGA-based emulation running on F2 FPGA instances and AFIs to share bitstreams and IP via the AWS Marketplace, with a 2-hour workshop demo… | ||
| Keynote: Blockchain, Cryptography, and RISC-V: A New Frontier in Open Development | Daniela Barbosa | 14m |
Argues that RISC‑V as software execution layer could replace complex VMs like the EVM to make smart‑contract execution simpler and faster, notes zero‑knowledge… | ||
| Keynote: Reimagining the Future of High Performance Computing Catalysed by RISC-V | Nick Brown | 15m |
HPC adoption of RISC-V shows concrete wins: a next-generation 64-core SG2042 family closes the gap with Skylake-class performance; Caliggo ships the first… | ||
| Keynote: RISC-V Opportunities at the Edge of AI | Makeljana Shkurti, Ed Doran | 14m |
Argues that RISC-V’s open, modular ISA plus vector and tensor extensions and domain-specific accelerators let edge devices run real-time AI where latency… | ||
| Demo: From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem | Darren Jones | 22m |
Emphasizes early architecture modeling and asks for instruction‑accurate and cycle‑accurate models plus SystemC to verify performance before silicon… | ||
| Collaboration Breakfast | Carl Perry, Flo Wohlrab, Jeffrey ‘Jefro’ Osier-Mixon, Nick Brown, Megan Lehn | 45m |
Panel lays out practical blockers and wins: finish the RVA23 profile and a volunteer-run certification so vendors ship conformant silicon; get more rackable… | ||
| Enhancing RISC-V Embedded Processor Performance Through Advanced Instruction F... | C. Basto, R. Ofir | 19m |
Claims a microarchitectural fusion that gives dual‑issue class performance by increasing fetch bandwidth, augmenting the decoder and adding a third register… | ||
| The Future of Ibex - A Production-grade, Open Source 32-bit RISC-V Core | John Thomson | 16m |
A production‑grade 32‑bit RISC‑V core used in multiple tape‑outs and shipping inside OpenTitan silicon that will protect Chromebooks and Google datacenter… | ||
| Enabling System Standby With RISC-V Platform | Fengxue Zhang | 19m |
Implements Suspend to RAM (S3) and Suspend to Disk (S4) on a LicheePi board based on the XuanTie TH1520, moving platform-specific power logic into a PCU close… | ||
| Unleash your RISC-V Future with Tenstorrent’s High Performance Ascalon RISC-V Processor... | T. Jones | 19m |
Ascalon is a production‑candidate RVA23 CPU core available for early access with early-access production-quality RTL and upstreamed GCC/LLVM support; silicon… | ||
| RISC-V Performance Delivered | Rabin Sugumar | 18m |
Claims a RVA23-compliant 8-core test chip with high-end OoO cores and an in-order AI core, taped out in months and sampling Q2 next year. Cores hit 4+ GHz… | ||
| Mission-Critical AI in Space and Sky: SWaP-Constrained Intelligence Wi... | D. Ojika, S. Mehrotra | 19m |
Unified RISC-V–controlled Agilex FPGA SoCs run deployed CV and LM models (YOLO, MobileNet, UNET) on an AI-native CubeSat FLAP-0 and a UAV ISR node SKY-0, with… | ||
| Democratizing Inference of Open-weight Models on RISC-V Manycore Acc... | R. Shaposhnik, T. Dadasheva | 19m |
Ainekko presents an open RISC‑V manycore inference platform: a low‑power 20–50 W chip family that scales 64–5000 cores, with a taped‑out card of 1,088 minions… | ||
| Running WebLLM in the Browser on RISC-V Toward Lightweight, Local AI Experiences | Kathy Giori | 17m |
Demonstrates a working WebLLM WebAssembly port on a full RISC‑V stack by enabling TensorFlow.js and ONNX Runtime Web backends and running inference in the… | ||
| Moving to RISC-V Vector: A Practical Journey of AI Operator Optimization | Guodong Xu | 24m |
Implemented MatMul, GELU and LayerNorm with SVE and RVV intrinsics on a SpacemiT K1 256‑wide RVV board and measured with perf and disassembly. Findings: vector… | ||
| Enhancing OP-TEE for RISC-V: Leveraging IOPMP and Enabling RTOS Integration | Bing Yu | 17m |
Andes extends OP-TEE on RISC‑V by wiring OP‑TEE to PMP/ePMP, MMU page isolation and a new IOPMP protects DMA to block bus-initiator transactions; upstream… | ||
| Optimizing Real-Time Application Requirements on ARC-V Processors Leveraging RISC-V Ex... | R. Collins | 15m |
Synopsys ARC-V implements custom RISC-V extensions that add a DMSI direct message signaling bus for deterministic interrupt delivery, a vectored table… | ||
| PQCP Support for RISC-V Vector, Future Keccak Extensions | Markku-Juhani O. Saarinen | 19m |
PQCP supplies production C implementations of ML-KEM, ML-DSA, SLH-DSA with formal type and memory-safety checks and CI running on ~300 targets; RISC-V Vector… | ||
| Making CHERI Accessible | Marno van der Maas, John Thomson | 20m |
LowRISC builds a CHERI-capable Sonata SoC plus an open FPGA evaluation board sold on Mouser and distributed as 100+ boards for experiments, using open PDK45… | ||
| Scaling Data Analytics Via Confidential Computing on RISC-V | Ravi Sahita | 21m |
Defines Supervisor Domains as a new privileged context with SDI cache tagging and MPT-based physical memory donation that prevents host access; maps… | ||
| CVA6-CHERI - An Open-source RV64Y Implementation for Commercialization | J. Woodruff, A. Joannou | 18m |
Implements CHERI on CVA6 as an RV64Y-compatible core, moving from an initial 58% logic overhead and 23% cycle-time penalty in the research prototype to… | ||
| Defending Against Transient Execution Attacks: Security Enhancements in XuanTie Microarchi... | X. Qin | 21m |
Xuantie implements a hardware‑software co‑designed security framework that partitions speculative buffers and flushes hard‑to‑partition state on context… | ||
| RISC-V for Gaming: Emulating X86 on RISC-V | Paris Oplopoios, felix86 | 14m |
A user‑space x86/x86-64 emulator for 64‑bit RISC‑V Linux called Philix86 implements a JIT recompiler, supports most ISA features up to SSE4.2, maps SIMD to RVV… | ||
| Keynote Panel: Winning the Future of RISC-V Automotive MCU Through Ecosystem Collaboration and Op... | Brandy Goolsby, Dan Mender, Rolf Kühnis, Rich Collins, Chris Thibeault | 45m |
Infineon commits its next-gen automotive MCUs to RISC‑V (announced at Embedded World) and the ecosystem shows concrete work: Synopsys and others supply RISC‑V… | ||
| Keynote: Awards Ceremony | 09m | |
Awards are presented across leadership and contributor categories naming Greg Olsson (Howard Leadership Award), David Weaver (Software Leadership), Fujian Fan… | ||
| Recent Developments in Optimizing Compilers for RISC-V | Jeff Law | 17m |
Uses Linux perf and PMU sampling to find hot, mispredicted branches and guide fixes at the binary level; example: a GCC global CSE loop replaced by a CTZ after… | ||
| Unlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-V | Mikhail R. Gadelha | 17m |
Upstream LLVM gains measurable real‑world wins: a new scheduling model for the space mak 60 plus a microbenchmark latency tool corrects instruction latencies… | ||
| SBI V3.0: Fueling the Next Wave of RISC-V System Software Innovation | Atish Patra, Anup Patel | 19m |
SBI v3.0 specifies concrete extensions: SSE preemptive events that inject RAS notifications and PMU-overflow samples even with interrupts disabled, MPXY… | ||
| Demo: More Than Point Tools: RISC-V Solutions | Larry Lapides | 14m |
Synopsys presents a full RISC‑V stack claim backed by numbers not marketing fluff: ASIP Designer and Platform Architect for architecture exploration, the… | ||
| The RISC-V Software Ecosystem: Primed for the Latest ISA Extensions | Andrew Jones | 19m |
Claims that Linux (including KVM) already supports the RVA23 profile and that the open-source ecosystem keeps pace with the ISA surge of tens of extensions per… | ||
| Tiling Support in the SiFive AI/ML Software Stack for RISC-V Vector-Matrix Extension (VME) | Min Hsu | 15m |
SiFive adds multi-tile matmul support to its IREE-based AI/ML stack that targets the RISC-V Vector-Matrix Extension (VME). VME uses an outer-product tile… | ||
| Unleashing ML Processing Power Through RISC-V Vectors: Applications, Implementation and... | B. Barker | 13m |
RISC-V Vector means big state and tricky verification: 32 vector registers, 7 CSRs and ~200 instructions and algorithmic scaling where VLmax scales across… | ||
| The RISE Project: Advancing RISC-V Software | Ludovic Henry, Nathan Egge | 19m |
The RISE Project invests more than €1M+ contracts to push upstream support for RISC-V across QEMU, OpenSBI, Linux kernel, GCC, LLVM and runtimes, and it… | ||
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