Kernel CXL Cache (safe) support
summary
CXL Type‑2 devices can cache host memory through a snoop cache per host bridge so the kernel must ensure a device’s advertised cache size fits the cache and track how many devices share it; virtualization exposes bigger risks because ATS alone is insufficient and devices can spoof translations, so safe passthrough needs to require IMU for passthrough or the host must allocate and enforce specific physical/IOVA ranges for caching, implying the kernel may need to extend DMA API and accept MMU involvement and performance tradeoffs.
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chapters (8)
- 0:00Introduction and goals
- 1:31CXL cache types explained
- 5:25Host memory caching concerns
- 8:38DMA API and CXL cache limits
- 12:10Virtualization and security issues
- 17:53Performance vs safety trade-offs
- 20:42Hardware attestation costs
- 21:03Q&A and summary
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