CXL Memory Tiering for heterogenous computing
summary
CXL adds capacity but hardware interleaving is rigid, hides NUMA and forces iso‑DIMM sizing; the proposed Linux changes push allocator‑level, software weighted interleave via allocator (per‑node or cgroup) so the kernel can steer pages between local DDR and CXL tiers. Tests on bandwidth‑bound workloads show about 35–40% improvement using tuned balances like 3:1 or 4:1 ratios. Patch sets and RFCs are in review and partially implemented.
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chapters (9)
- 0:00Introduction and agenda
- 1:06Memory demand and scaling challenges
- 3:11CXL memory expansion overview
- 7:29Hardware vs software interleaving
- 10:23Kernel patches for weighted interleaving
- 15:31Benefits of software interleaving
- 19:24Hardware vendor perspective
- 21:52Call to action for Linux community
- 24:50Q&A and next steps
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