Taming the Incoherent Cache Issue in Confidential VMs
summary
AMD's SME_COHERENT hardware flag does not cover device DMA, so confidential guest pages can leave dirty CPU caches and later corrupt host memory (CVE-2022-0171). Upstream currently flushes caches whenever guest mappings are removed, causing large performance regressions on SEV-SNP workloads. Two concrete paths are explored: SME_COHERENT lacks CPU-device DMA coherence; use mmu_notifier "reason" filtering to flush only on true deallocation, and/or replace wbinvd with VMPAGE_FLUSH MSR to avoid machine-wide flushes. A mmu_notifier-based patch reduces unnecessary flushes but hits overloaded notifier reasons, so adding finer-grained reasons is necessary.
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chapters (5)
- 0:00Introduction to cache incoherence
- 3:30AMD hardware fixes and gaps
- 6:18MMU notifier solution approach
- 11:13Performance and security trade-offs
- 15:00Q&A and future considerations
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