CXL Type-2 core support
summary
Describes which CXL Type‑2 features exist upstream and which still need work: P2P, Back‑Invalidate, Cache‑ID configuration are required for accelerators, and Dan Williams' region split landed in mainline but more structure separation and a small upstream fix are proposed. QEMU work provides a quu dummy accelerator for testing but effort favors adding cxl test cases. Notes gaps around RAS/RAZ handling, mailbox vs in‑band errors, and requests real vendor devices to exercise type‑2/type‑3 needs.
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chapters (9)
- 0:00Introduction and motivation
- 1:05Type 1 vs Type 2 CXL overview
- 2:12Current Type 2 core support
- 3:37Core requirements for accelerators
- 5:23Testing and validation approach
- 7:55Intel FPGA Type 2 work
- 9:18First-mover advantage for drivers
- 10:01RAS handling and core separation
- 13:10Transition to DCd discussion
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