Expanding the Memory Limits with CXL Software Stack
summary
Claims that adding four Micron CXL controllers with 256 GB modules raises per‑core bandwidth from ~6 GB/s to ~14 GB/s and boosts system capacity by ~133%. Describes Linux support: CXL Type 3 devices expose memory as separate NUMA nodes, kernel-driven page migration and NUMA balancing perform tiering between DDR, CXL and storage, and a weight-based interleaving policy lets allocations be split (NPS1 = 50/50, NPS2 ≈ 66/34, NPS4 ≈ 80/20). Mentions a shared‑memory filesystem (farmFS) on GitHub and features merged into 6.9.
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chapters (16)
- 0:00CXL memory expansion on Linux
- 1:04What is CXL
- 2:36CXL data center memory
- 5:04CXL protocols and devices
- 7:58CXL capacity and bandwidth
- 12:40Memory tiering with CXL
- 16:38NUMA and memory tiering
- 19:29Page migration in tiering
- 22:25Kernel vs app-managed CXL
- 25:14Memory interleaving for bandwidth
- 28:10Interleaving configurations
- 33:14Weight-based interleaving policy
- 36:51CXL memory sharing and pooling
- 38:41FarmFS for CXL shared memory
- 40:10CXL driver stack and kernel support
- 41:14Conclusion and future
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