CPU Isolation and IPI interference

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" summary

CPU isolation fails because housekeeping CPUs still send IPIs for things like static key updates and TLB invalidations; observed with a kernel compile plus hackbench generating cross-CPU interference. The mitigation implemented defers kernel-only work to defer to kernel entry using context tracking and early-entry assembly checks; static-key deferral works, TLB deferral is “horrendous” and slows entry so far. Prototype code exists; hardware fixes (AMD invalidate broadcast, Intel remote action request) would remove much of the pain. unconditional TLB flush is a fallback but costly.

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" chapters (13)

1. 0:00Introduction to CPU isolation
2. 1:03IPI interference on isolated CPUs
3. 2:30Deferring kernel operations
4. 4:36Discussion on IPI sources
5. 6:24Context tracking and TLB flushes
6. 8:12User space isolation challenges
7. 10:40Hardware support for TLB flushes
8. 12:10API for CPU isolation
9. 13:53High-frequency trading use case
10. 16:19Per-CPU memory pressure
11. 17:25Memory bus contention risks
12. 18:29TLB flush and CR3 switching
13. 19:16Q&A and conclusion