Declaring WARL on the ISA string
summary
WARL behavior in RISC-V causes KVM to probe CSRs by writing and reading back values, which breaks virtualization performance and consistency; the concrete fix is to declare legal CSR ranges (e.g., SATP modes and ASID width) and publish them once instead of probing each boot. Proposal uses the Unified Database YAML to derive ISA DT from UDB YAML and expose it via SBI call or DT/ACPI blob so guests see stable, pre-benchmarked capabilities.
AI-written summary · about
chapters (5)
- 0:00Introduction to ISA string issues
- 4:43Problems with virtualization and WARL
- 7:12Solutions for better ISA description
- 11:49Discussion on ISA standardization
- 23:21Q&A and closing remarks
related talks
30mThe Odyssey of HWCAP on RISC-V platforms
24mReliability, Availability, and Serviceability (RAS) on ARM64 status
36mRISC-V Bug Hunting
27mTuning in-kernel routines on RISC-V
50mInitializing RISC-V A Guided Tour for ARM Developers
30mAIA Virtualization in KVM RISC-V
34mRISC-V ACPI and UEFI Updates
26mThe Big-endian RISC-V Linux Adventure