Microconference for resctrl
summary
Microconference reports concrete kernel work: resctrl is adding ARM MPAM integration, a new schemata layout that separates resources from controls, and reads hardware that exposes memory‑bandwidth values as finer granularity (examples show MB granularity 1..511 or fixed‑point). Intel region‑aware maps physical address ranges into up to four regions and stalls counters per region for MBM; AMD raises counters to 64, adds GMBA and PL0 association to bound groups and let hardware swap kernel/user limits without MSR overhead. Missing pieces include KVM virtualization handling and a proposal for GPU/CXL memory as CPU‑less NUMA nodes needing new MB domain IDs.
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chapters (10)
- 0:00Introduction to resctrl microconference
- 1:03Enhanced resctrl schema descriptions
- 9:32Region-aware memory bandwidth on Intel
- 20:09AMD’s global memory bandwidth allocation
- 28:01MPAM hardware feature challenges
- 35:04Qualcomm’s MPAM implementation status
- 38:39GPU memory node support in resctrl
- 42:37Discussion on resctrl for RISC-V
- 59:32Future of resctrl and RISC-V features
- 1:03:48Q&A and closing remarks
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