Cooperation between CPU and system level cache by using MPAM

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" summary

MPAM PartID tags get translated at a small hardware-backed translation layer that maps incoming PartIDs to SLC-specific IDs via mapping tables programmed over SCMI and exposed (proposal) as a mappings resource in resctrl. Current silicon simulates only two SLC partitions so system-wide partitions remain constrained; driver work is in progress. A microbenchmark (two parallel bcopy tasks, 16 MB) that excludes the noisy task from SLC shows about an 8% throughput improvement.

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" chapters (7)

1. 0:00Introduction to MPAM
2. 1:50System level cache challenges
3. 4:00Translation layer solution
4. 5:24Use case isolation
5. 6:06Complex partitioning strategies
6. 7:32Performance improvements
7. 8:35Q&A session