Latch-Up 2024
2024-04-19..2024-04-21
Cambridge, United States
Latch-Up ·
[Latch-Up 2024, Latch-Up 2025, Latch-Up 2026]
who it's for
open-source silicon engineers, eda tool developers, hardware engineers, fpga engineers, embedded systems engineers, hardware security researchers, hardware educators
topics
custom GPTs for hardware design; IHP open PDK 130nm; Universal Memory Interface (UMI); RISC-V open-source silicon flows; timing-aware Verilator simulation; Chisel 6 MLIR FIRRTL pipeline; CHERI capability-based architecture; Tiny Tapeout open silicon; OpenROAD place-and-route flows; hardware foundation models (Arch Gym); wave pipelines in FPGAs; tclint EDA linting
| title | author | length |
|---|---|---|
| Accelerating Hardware Design with Custom GPTs | Shvetank Prakash | 03m |
A plugin connects CFU Playground to OpenAI CustomGPTs and ChatGPT to automate profiling, generate tiny-ML accelerator RTL, and run synthesis and physical… | ||
| OSHHISS Open Source for Hybrid Hetrogenous Integrated Semiconductor Systems | John Goodenough | 03m |
Call for collaborators to build open source design patterns and EDA toolflows that turn materials-and-device prototypes into integrated products, targeting… | ||
| ABC: The Way It Should Have Been Designed | Alan Mishchenko | 25m |
ABC dates from 2005 and centers on And-Inverter Graphs (AIG) as a unifying data structure for synthesis, mapping and equivalence checking, with iterative… | ||
| UMI: Universal Memory Interface | Andreas Olofsson | 25m |
UMI is a transaction‑based memory interface that replaces wide wire buses with packetized request/response messaging, claiming to scale to chiplets and SoP… | ||
| From an Open-Source ISA to Open-Source HW to Open-Source Silicon | Luca Bertaccini | 19m |
PULP describes a working pipeline from an RISC-V ISA to open RTL IPs to a full chip built with IHP 130 nm open PDK and open-source EDA (yosys and OpenROAD)… | ||
| Transparent Checkpointing for Fault Tolerance in RISC-V | Aayushi Gautam | 18m |
DMTCP is ported to RISC‑V Linux on a BeagleV PolarFire SoC and resumes simple and TCP‑socket C++ programs from checkpoints (a counter restarts at the saved… | ||
| Sonata: A development platform to enable exploring the use of CHERI for embedded applications | Hugo McNally | 15m |
Sonata is an open-source development platform that puts CHERI-derived Chariot protection on an Artix‑7 FPGA SoC with an Ibex core, HyperRAM execution, RP2040… | ||
| Where Community Powers Innovation | Mohamed Kassem | 04m |
Company claims it turns open source silicon flows into shipped products by lowering cost and complexity for niche builders, backed by a working platform that… | ||
| Open source RTL verification with Verilator | Karol Gugala | 24m |
Verilator now supports timing-aware simulation via a new coroutine scheduler and compiled UVM SystemVerilog constructs so UVM code transpiles to C++ and runs… | ||
| Architecture 2.0: Toward Open Source Foundation Models and Datasets for Hardware Design | Vijay Janapa Reddi, Shvetank Prakash | 22m |
Argues for “Architecture 2.0”: build open, hardware-specific foundation models trained on open-source datasets (RTL, netlists, layouts, metrics) to cut cost… | ||
| Chisel 6 and beyond | Jack Koenig | 23m |
Chisel 6 moves the FIRRTL implementation to an MLIR-backed Circuit/ferTool pipeline for much faster, lower-memory compilation and faster feature work. New… | ||
| Zeno: An Open-Source Scalable Capability-Based Secure Architecture | Alan Ehret | 02m |
An open-source, capability-based architecture adds hardware-attached metadata to registers and memory so language-level sizes, shapes and access permissions… | ||
| Attempts to design hardware using dafny | Ben Reynwar | 03m |
Uses Dafny with SMT solver to write programs that generate hardware and prove properties about them; attempts include a function that turns a circuit struct… | ||
| Teaching Modern EDA using a Tapeout-Centric University Course | Anish Singhani | 21m |
Course runs four semesters with ~60 students and gets every student to tape out a design using tiny tapeout (≈$150 MPW slots) or a shared MPC chip built on the… | ||
| Tiny Tapeout: custom silicon open to all | Pat Deegan | 26m |
Tiny Tapeout provides inexpensive, educational chip runs that take Verilog to manufactured silicon using open Lane/open road toolchains, Magic and xschem/xcam… | ||
| IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead | Frank Vater | 16m |
Publishes an SG13G2 130nm BiCMOS Open Source PDK on GitHub (first data 2023, ~203 comments) that provides process specs, layout manual, a working DC rule deck… | ||
| CACE Study: Open source analog and mixed-signal design flow | Tim Edwards | 24m |
CACE (Circuit Automatic Characterization Engine) is an open source Python flow (available via pip install cace) that verifies analog/mixed‑signal designs using… | ||
| RF Front-end receiver design for 2.4GH/5GHz WiFi application | Jabeom Koo | 21m |
Two tape-outs use efabless open-source flow and SkyWater 130nm PDK to implement an LNA+mixer+VCO for 2.4/5GHz Wi‑Fi, targeting June chip delivery; design shows… | ||
| Beyond EDA lies Edalize | Olof Kindgren | 18m |
Edalize is a standalone Python library that programmatically builds and runs EDA workflows by turning an Edam format description into tool-specific setups… | ||
| A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation | Steve Hoover | 20m |
TL‑Verilog shows concrete progress: 15 GSoC projects since 2018 (two more under CHIPS Alliance this year) produced working artifacts — a configurable RISC‑V… | ||
| Open Source Hardware: Hacking Silicon for Fun (instead of profit) | Troy Benjegerdes | 14m |
Argues that the open silicon stack now makes small-scale chip fabrication practical, claiming less than $700,000 to start building useful parts, showing… | ||
| Switchboard: Calling All Hardware Models | Steven Herbst | 16m |
Switchboard wires RTL, FPGA, C++ and Python models via simple 52-byte packet messages over mmap-backed shared-memory queues that present a ready/valid… | ||
| Spade: An HDL Inspired By Modern Software Languages | Frans Skarman | 18m |
Spade is an open source EUPL‑1.2 HDL that adds native pipelining (declare pipeline depth, use explicit r registers; compiler retimes and errors when values are… | ||
| HDLAgent, Enhancing Hardware Language in the age of LLMs | Jose Renau | 24m |
A toolchain called HDLAgent wraps LLMs with self-reflection, retrieval-style context and compiler grounding to iterate on generated HDL, auto-create… | ||
| PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface | Matthew Ballance | 16m |
PyHDL-IF provides an object-oriented Python↔HDL bridge that is 99% pure-Python with a tiny precompiled C++ bootstrap, avoiding per-user generated wrappers. It… | ||
| Open-source resources for learning the Bluespec HL-HDLs | Rishiyur Nikhil | 23m |
Free, open-source course materials accompany a new ~300‑page textbook and a single GitHub repo with PDFs, sources, Makefiles and testbenches; materials teach… | ||
| Giving Students A Byte of Open-Source: Advancing Hardware Education | Ethan Sifferman | 18m |
Argues SystemVerilog becomes teachable end-to-end using open-source tooling: FuseSoC, Verilator, Yosys, CVA6, Ibex and DigitalJS for interactive netlist… | ||
| Riding The Wave: Building Wave Pipelines in FPGAs | Rice Shelley | 20m |
Builds a two‑stage wave‑pipelined cellular‑array multiplier on Xilinx 7‑series FPGAs using SpinalHDL and manual placement with RLOC origin / RPM constraints… | ||
| MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL | Tobias Strauch | 20m |
Claims a new language PDVL enables reusable, aspect-oriented transaction-level deductive verification by compiling transactions into Gallina so proofs run in… | ||
| Artifact Evaluation for the Field Programmable Gate Array Community | Miriam Leeser | 19m |
Artifact Evaluation is established for FPGA papers: the process introduced AE to the FPGA community five years ago and now issues ACM/IEEE badges, requires a… | ||
| Towards Cycle-accurate Simulation of xBGAS | Jie Li | 19m |
Claims a cycle-accurate SST simulator (REV-xBGAS) that models xBGAS by extending the Rave CPU component, adding an extended register file mapped to base RISCV… | ||
| ChipWhisperer: Past & Future of a FPGA-based Research Tool | Jean-Pierre Thibault | 03m |
An open-source, FPGA-based single-channel oscilloscope measures tiny power differences to perform side-channel attacks and ships with schematics, FPGA… | ||
| Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture | Mert Side | 20m |
Retrofits the xBGAS runtime to CHERI-enabled ARM Morello by translating RISC‑V xBGAS semantics into ARM equivalents and simulating distributed PEs with pthread… | ||
| CoreScore like never before | Olof Kindgren | 02m |
CoreScore measures how many RISC‑V SERVE cores fit into various FPGAs and claims a surprising top result of 10,000 RISC‑V cores packed onto a large AMD board… | ||
| Clean up your EDA flows with tclint | Noah Moroze | 03m |
tclint statically analyzes Tcl EDA flows and flags concrete issues such as missing dollar signs, forgotten command-substitution brackets, and missing… | ||
| Cohort: Software-Oriented Acceleration for You, Me, and Our Heterogeneous SoCs | Nazerke Turtayeva | 13m |
Cohort is a platform that exposes accelerators through a uniform high-performance shared memory queues API plus a per-accelerator hardware wrapper that… | ||
| CedarEDA for open source silicon | Keno Fischer | 23m |
A Julia-written analog simulator and optimizer compiles spice and Verilog into a common IR and generates JIT machine code for CPU (GPU planned) and claims… | ||
| Surfer - An Extensible and Snappy Waveform Viewer | Frans Skarman | 02m |
Surfer is an extensible waveform viewer that runs in the web browser and connects to an HDL toolchain so traces keep their types instead of becoming raw bits… | ||
| Tim's Silicon Presentations | Tim Ansell | 04m |
Quick status update on open PDKs and community tooling lists the actual foundries and numbers: sky130 and globalfoundries 180 are joined by an IHP 130 nm PDK… | ||
| Caster: An Open-source E-Ink Controller | Wenting Zhang | 18m |
Caster is an open-source E‑Ink controller IP with fully published RTL, PCB and enclosure designs and an FPGA reference monitor built on a Spartan‑6. It runs at… | ||
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