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Jie Li

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CacheSlide: Unlocking Cross Position-Aware KV Cache Reuse for Accelerating LLM ServingFAST '262026-02-24
CacheSlide: Unlocking Cross Position-Aware KV Cache Reuse for Accelerating LLM Serving Yang Liu and Yunfei Gu, Shanghai Jiao Tong University; Liqiang Zhang…
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Towards Cycle-accurate Simulation of xBGASLatch-Up 20242024-04-19
Claims a cycle-accurate SST simulator (REV-xBGAS) that models xBGAS by extending the Rave CPU component, adding an extended register file mapped to base RISCV…
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ParaRC: Embracing Sub-Packetization for Repair Parallelization in MSR-Coded StorageFAST '23: 21st USENIX Conference on File and Storage Technologies2023-02-21
ParaRC leverages sub-packetization of MSR codes to parallelize sub-block repairs, models the problem as a colored graph called a PEC DAG to expose the…
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Tetris: Memory-efficient Serverless Inference through Tensor SharingUSENIX ATC '222022-07-11
Tetris claims an order‑of‑magnitude drop in memory footprint for serverless inference by actually sharing immutable model tensors across co‑located containers…
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