Microwatt Microarchitecture
summary
An open-source Power ISA soft core written in VHDL implements most integer user-space instructions and targets simulation and FPGA use, using a Wishbone memory interface. The design stays compact at under 10,000 lines so the whole microarchitecture is inspectable; most integer ops are single-cycle, the divider takes 10–66 cycles and the multiply ~18-cycle multiply, so multiply/divide are slow. Missing pieces: MMU, supervisor mode, interrupts, reliable unaligned loads, and full FP support needed to run Linux.
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chapters (11)
- 0:00Introduction
- 2:23Instruction set
- 5:51Pipeline structure
- 9:05Register file
- 15:14Fetch
- 17:13Decode
- 18:59Cache
- 19:43Execution
- 22:07Instructions
- 23:21Todo list
- 27:24Patents
