Coriolis RTL-to-GDSII Toolchain

" summary

Describes a free/open-source RTL-to-GDSII flow using Yosys for HDL synthesis to an ASIC standard-cell library, then Coriolis2 for placement, routing and basic timing closure aimed at mature nodes (≥130nm). Covers progress made over the past year and specific planned improvements and new features for 2022.

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