CPU-Level Optimizations
summary
Covers techniques to squeeze maximum performance from a single CPU/core when extra servers aren’t an option, focusing on hardware-aware optimizations. Topics include CPU cache usage, instruction‑level parallelism, false sharing, branch prediction, and SIMD instruction sets like SSE/AVX, with practical approaches to speed up otherwise hard-to-optimize programs.
AI-written summary · about
chapters (10)
- 0:00Introduction
- 1:55Optimization methodology
- 4:06Finding bottlenecks
- 9:08Code optimization example
- 14:15Cache and performance
- 20:24Branch prediction
- 23:17How CPU cache works
- 27:15Parallelism issues
- 30:51CPU knowledge importance
- 31:59Q&A
related talks
01h 50mUnlocking Modern CPU Power - Next-Gen C++ Optimization Techniques
15mPrinciples and Methodologies for Serial Performance Optimization
44mFastware
42mAdventures in Efficiency and Performance
23mBeating the Benchmarks: Co-evolving the ISA and Development Tools
51mDesigning for Performance
01h 02mFastware
01h 04mThe Future of Fast Code: Giving Hardware What It Wants