Unlocking Modern CPU Power - Next-Gen C++ Optimization Techniques
summary
Covers how CPUs in the last ~10 years move to multi‑die tiles (e.g., 15 cores per tile), ~40B transistors, bigger caches and longer pipelines that make old tweaks hurt or help differently. Random access can be catastrophically slow—38× slower list iteration vs vector—and branch mispredictions cost ~4–7×. NUMA makes remote memory ~50% lower remote bandwidth and UPI about 160 ns latency; page migrations cause TLB shootdowns that dominate kernel time. A per‑node counter redesign raises a threadpool from 2M to 42M tasks/sec.
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chapters (16)
- 0:00Evolution and complexity
- 5:48Avoiding common pitfalls
- 8:46Superscalar execution
- 17:01Prefetching and caching
- 23:27Pipelines and branching
- 30:59Branchless optimization
- 38:46Concurrency and bottlenecks
- 45:44Understanding NUMA
- 55:15Data sharing challenges
- 58:45NUMA optimization techniques
- 1:05:40Advanced contention handling
- 1:11:17Thread pool optimization
- 1:19:38NUMA migration issues
- 1:25:22TLB and OS impacts
- 1:33:26IO and CPU throttling
- 1:36:42Conclusion and profiling
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