OpenPOWER Summit NA 2021
as the organisers put it
REGISTER explore the schedule OpenPOWER Summit NA 2021 is a wrap! Thank you to all of the attendees, speakers, and sponsors that joined us virtually this year. To experience the best of the event…
| title | author | length |
|---|---|---|
| Welcome | James Kulina | 11m |
Announcement describes OpenPOWER shifting from license-based to open-source processes, adopting open source EDA and Chips Alliance partnerships, shipping a… | ||
| Software-driven Hardware in the Data Center: LibreBMC, Renode, RowHammer... | Michael Gielda | 16m |
Open source FPGA BMC implemented as a LibreBMC FPGA dcscm module runs Zephyr or Linux, supports external TPMs and migrates between Artix7 and ECP5 with full… | ||
| Strategies for CXL’s success in a world of proprietary Coherent... | Allan J. Cantle | 14m |
Argues that adding small two‑port shared memory buffers and exposing local HBM/OMI channels as CXL-connectable resources lets CXL grow alongside proprietary… | ||
| What it is, why it’s here, and how you can get... | Kim McMahon | 13m |
Open Hardware Diversity Alliance forms in August 2021 with RISC‑V, Chips Alliance, OpenPower Foundation, Western Digital and IBM, launches September 2021, and… | ||
| Building an Open Source Hardware Ecosystem: From Foundations to Rooftops | Rob Mains | 15m |
CHIPS Alliance describes concrete steps: an open PDK (notably SkyWater open PDK) drives a surge in developer interest, 38 member companies collaborate, and… | ||
| AI acceleration in POWER10 | Rajalakshmi S, Satish Kumar Sadasivam | 25m |
POWER10 adds Matrix Multiply Assist instructions with 8 512-bit accumulators and a 4x4 float32 micro-kernel that produces 16 multiplies per instruction… | ||
| ISA curriculum | Abhinandan S P | 39m |
Course describes a concrete POWER ISA curriculum that teaches students to design an SoC end-to-end: front-end RTL with SystemVerilog, integrate and verify IP… | ||
| Beyond Machine Boundaries: Experience with Memory Disaggregation | Felix Eberhardt, Andreas Grapentin | 45m |
Prototype uses ThymesisFlow on two IC922 Power9 servers with AlphaData ADM9V3 FPGAs connected back-to-back, exposing remote memory via either a kernel mappable… | ||
| A Vision for Transforming 21st-Century Pedagogy via Open Standards | Wu Feng | 41m |
Proposal replaces mixed ISAs with a vertically integrated curriculum centered on OpenPOWER ISA, adds an OpenPOWER case study to every chapter of Computer… | ||
| Next-gen Dynamic UAV using Power9 Systems | Sri Kamani, Sashank, Deepthi, Barat. T, Adithya Gopan | 47m |
A drone system classifies fire vs non‑fire images using a convolutional neural network trained on a large mixed dataset from forestry departments and public… | ||
| Bayesian Optimization Accelerator | Xinghong He | 46m |
An appliance-based toolkit running on an AC922 appliance (RHEL) exposes a minimal HTTP SDK and uses Gaussian processes with many kernel and acquisition… | ||
| A course on Accelerating Big Data Analytics Application with... | Arghya Kusum Das, Peter Hofstee | 43m |
Course explains how OpenCAPI FPGA engines accelerate big data by connecting FPGAs to host memory, uses Fletcher with Apache Arrow to build platform‑agnostic… | ||
| AI APPLICATIONS ON POWER9 SYSTEM | Sridhar Ramasubramanian, Vaibhav Raja | 43m |
Claims that POWER9 with NVIDIA Tesla V100 GPUs runs enterprise ML/DL workloads that would otherwise need hundreds of CPUs, citing a single GPU being 100 CPUs… | ||
| A Course on Machine Learning for Software Developers | Arghya Kusum Das | 35m |
Course material built with four industry partners (Facebook, Fractal, Fidelity, IBM) teaches beginner developers end-to-end ML workflows with working… | ||
| Fabless SoC | A C Venkatesh | 55m |
An academic fabless SoC named ANANTH uses the open POWER A2O core integrated with an AXI4 interconnect and Verilog RTL; peripherals implemented and… | ||
| Draft SVP64 in-place Matrix Multiply and FFT / DCT | Luke Kenneth Casson Leighton | 44m |
Claims an SVP64 prefix extension that runs in-place matrix multiply up to 128 FMACs with only a 3-instruction hot loop (shape setup, remap, FMAC), removing the… | ||
| Coriolis2 -- A FOSS RTL to GDSII toolchain | Jean-Paul Chaput | 01h 04m |
Coriolis2 converts HDL through Yosys into an ASIC netlist then performs placement, global and detailed routing, basic timing closure and GDSII output; the… | ||
| E4S: Extreme-scale Scientific Software Stack | Sameer Shende | 41m |
E4S provides a curated HPC distribution built with the Spack package manager, delivering both bare-metal installs and container images and hosting a binary… | ||
| A fully open source memory controller targeting LPDDR4/5 for FPGA and ASIC us... | Tim Ansell | 48m |
A fully open source memory controller called LightDRAM targets LPDDR4/5 and other DDR standards, generates optimized Verilog from a Migen-based generator, and… | ||
| Prepare yourself to switch computing to Open Hardware Power Architecture | Roberto Innocenti | 37m |
Project began in 2014 and aims to deliver three prototypes of an Open Hardware GNU/Linux PowerPC laptop by late 2021; design moves from schematic to… | ||
| Differential Software Solutions on HPC and IBM Power Architecture | Ander Ochoa Gilo | 42m |
Claim: IBM Power9 nodes run distributed in‑memory AI training at supercomputer scale using RDMA/Infiniband and NVLink, not just CPUs. Demo builds a Cloud Pak… | ||
| Introduction to the LibreBMC project | Todd Rosedahl | 24m |
LibreBMC replaces the AST2500 BMC ASIC with a soft processor on low-cost FPGA hardware (Arty/RD/A7 family) running Microwatt and OpenBMC, plugs into the AC922… | ||
| Working Groups Walkthrough | Toshaan Bharvani | 24m |
OpenPOWER lists over 300 members and reorganizes working groups from specs to deliverables: technical WGs produce ISA and compliance test harnesses (ISA now… | ||
| coreboot on POWER9 | Piotr Król | 49m |
Coreboot is ported to POWER9 on Talos II and Talos II Lite, producing a working boot path that replaces the 1.7M-line hostboot stack with a much smaller… | ||
| Testing Framework to port and optimize SIMD library to Systems | Daisuke Oka | 15m |
Framework ports Intel x86 SIMD intrinsics to OpenPOWER ISA by running the same tests on two machines connected over the network and asserting identical… | ||
| High-Performance and Scalable Middleware for HPC and Deep... | Dhabaleswar K (DK) Panda, Donglai Dai | 45m |
MVAPICH2 and MVAPICH2-GDR integrate with Horovod to run ResNet50 on 1,536 GPUs and achieve about 0.42M images/sec (ImageNet training in ~4.5 minutes)… | ||
| The Toy-SRAM Project | Robert Montoye | 29m |
An open-source multiport memory system replaces bespoke register-file circuits with a replicated 10T SRAM cell that separates reads and writes, enabling lower… | ||
| Open Hardware through Open Power SBC | Manuel Virgilio | 16m |
A single-board computer called Jungle targets the NXP T1040 SoC and emphasizes minimal parts with lots of connectivity: DDR4, basic HDMI (no GPU), two 1GbE +… | ||
| Collaboration Walkthrough | Toshaan Bharvani | 25m |
A monolithic WordPress/Causeway site is replaced by a modular open source stack running on Power8/9 that separates public and member surfaces, automates… | ||
| A Complete Re-Think for Memory Config... | Jim Handy, Brian Allison, Tanj Bennett, Tom Coughlin | 46m |
Panel claims memory interfaces consume orders more energy than compute and that redesigning them unlocks new architectures: local DRAM interfaces cost about… | ||
| Closing Remarks | James Kulina | 04m |
Closing remarks summarize a push to grow the OpenPOWER ecosystem with concrete, developer- and hardware-focused initiatives, public-facing SIG work groups that… | ||
| SoC in Hours - A Power Chat | Manikandan Nagarajan, Vinod Bussa, Dr. Sumalatha, Abhishek Sharma | 03h 10m |
Claims a full OpenPOWER SoC flow that builds a working soft core and produces tapeout files in hours, using the Microwatt open core and Libre‑SoC toolchain. It… | ||
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