CXL hotplug: spec to reality
summary
CXL 1.1 lacks hotplug, so FPGA-based endpoints that reprogram the bitstream rely on PCIe hot unplug ~30s or full reboots (minutes) to avoid host-link corruption; that makes iterative development and production updates impractical. Two practical routes appear: a kernel best-effort hotplug hook that rescans devices with caveats around host snoops and firmware support, or forcing endpoints to use partial reconfiguration and guaranteed miss behavior on the PCI block. Host CPU snoop timing, firmware handlers and SMR support determine whether either approach actually works.
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chapters (6)
- 0:00Introduction and overview
- 2:23Spec roadmaps vs reality
- 6:40Use cases with FPGAs
- 8:45Hot plug challenges in CXL
- 13:19Proposals for hot plug support
- 22:18Q&A and discussion
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