CPU isolation vs jailbreaking IPIs
summary
Tracing shows isolated CPUs still receive disruptive IPIs caused by a few concrete kernel behaviors: a rapidly flipping static key from ntpd socket timestamping, TLB flushes and the x86 instruction‑patching three‑IPI sequence. Work uses coccinelle and tracing to classify ~400 SMP call sites, lands context‑tracking in 6.0, and applies deferral patches (Peter/Nicolas) that eliminate interference for the tested workload. Proposed fixes are an intent‑expressing API to defer SMP calls where safe, added logging/tracepoints, and architecture‑specific fallbacks like remote MSR reads.
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chapters (10)
- 0:00Introduction CPU isolation
- 1:26IPI interference in benchmarks
- 4:56Analyzing SMP call sites
- 10:15Patterns of IPI usage
- 13:08Casual use cases and fixes
- 17:24Q&A on RCU and IPIs
- 23:53Perf events and IPIs
- 27:01Deferral patches and performance
- 31:06TLB invalidation and IPIs
- 36:19Architecture-specific challenges
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