CXL and confidential computing
summary
CXL exposes HPA physical addresses so devices can access any host memory unless access control is implemented per device, and many memory modules ship with ARM cores that can read or tamper with data. The channel needs per-message integrity tags with counters and payload encryption, but CXL’s multi-path fabric forces a choice: point-to-point encryption trusts every intermediate switch while true end-to-end keys face a state‑explosion (per‑stream key and metadata) that current silicon won’t afford. Implementing ATS/IOMMU-like filtering is possible but rarely done.
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chapters (10)
- 0:00Introduction to CXL and confidential computing
- 3:11Pyramid of trust in enclaves
- 7:08Security for CXL device communication
- 12:25Overview of CXL protocol
- 15:51Risks of CXL memory devices
- 20:54Physical vs software attack threats
- 22:00Peer-to-peer device communication
- 23:03Firmware auditing challenges
- 25:11CXL device types and security
- 27:39Summary and Q&A
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