Confidential Computing for RISC-V-based Platforms
summary
Proposes a RISC‑V confidential VM model implemented via the H (hypervisor) extension with a small TSM running in HS mode that enforces isolation, measures pages (measured vs clear), and places second‑level page tables in confidential memory backed by optional memory‑controller encryption. Defines SBI/TSM intrinsics for VM lifecycle, introduces a new physical memory attribute, and ties attestation to a TCG DICE chain. A prototype TSM proof‑of‑concept exists online.
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chapters (8)
- 0:00Introduction to confidential computing
- 1:03Security properties and threat model
- 5:32Reference architecture overview
- 13:18Q&A on ISO changes
- 15:02Host software interfaces
- 22:50Attestation model
- 27:27Memory mapping security
- 30:13Call to action and conclusion
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