DNNs on FPGAs
summary
Covers concrete FPGA strategies: loop unrolling, tiling and interchange with a worked case that maps about 3,136 PEs in an output‑stationary MAC array, plus tradeoffs that make partial sums local to avoid DRAM traffic. Shows tool paths: HLS/OpenCL and automatic RTL generators, cites FIN bnn for binary networks, and demonstrates training/throughput gains using Stratix 10 MX with HBM where low-batch training and on-chip weights cut DRAM bandwidth and improve energy efficiency.
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chapters (22)
- 0:00Introduction
- 1:25Outline
- 3:47DNN Algorithms
- 5:22Types of DNN Algorithms
- 6:02What is Deep Learning
- 7:08Image Classification
- 9:51Convolutional Networks
- 11:56Imagenet Data
- 14:23Hardware
- 15:17New papers
- 16:07GPU vs ASIC
- 20:10FPGA basics
- 20:50FPGA evolution
- 25:18DNN Inference
- 28:43Loop Optimization
- 34:53Summary
- 37:30Objectives
- 42:45Data reuse
- 45:43External memory access
- 49:45High level concepts
- 56:14Case study
- 58:34Mstar
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