Introduction to Neuromorphic Computing
summary
Introduces a memristor-based neuromorphic chip with memristor crossbar arrays and a spiking processing engine that maps convolution kernels via a PipeLayer pipeline; demonstrates MNIST/CIFAR inference with measurable accuracy loss versus ideal analog (small), but claims much higher area and energy efficiency on silicon. Shows single-spike coding and temporal encoding hardware that trades latency for power, uses group-lasso structured sparsity and low-rank clipping to get real hardware speedups, and reports an in-situ retraining trick that substantially extends device lifetime under resistance drift.
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chapters (25)
- 0:00Introduction to neuromorphic
- 1:45Defining intelligence and AI
- 6:12Technology landscape advancements
- 10:39Evolution of neural networks
- 15:38AI chip design challenges
- 20:16Neuromorphic computing concepts
- 26:26Characteristics of neuromorphic
- 32:45Neural and network models
- 38:51Hardware implementation trends
- 44:03Neuromorphic hardware examples
- 47:43Emerging memory devices
- 52:08Software stack requirements
- 55:54Memristor-based chip research
- 1:02:06Spiking processing engines
- 1:07:05Hardware design challenges
- 1:13:30Non-linear activation functions
- 1:18:46Spiking conversion techniques
- 1:24:03Accelerator design parallelism
- 1:26:28Algorithm-hardware co-design
- 1:31:57Compression techniques
- 1:37:17Reliability and drift
- 1:40:41Optimization and challenges
- 1:45:38Conclusion and Q&A
- 1:51:54Audience questions
- 1:55:54Closing remarks
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