Memory-Centric Computing

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Memory movement dominates energy and latency — measured workloads spend ~60% of device energy on data movement — so designs put simple computation into memory and near-memory controllers. Measured phenomena include the rowhammer vulnerability (new DRAM chips flip bits with as few as ~4,800 double‑sided activations and many chips show >80% susceptibility) and retention/refresh costs. Prototypes and simulators show RowClone cuts a 4KB copy from ~1000ns/3.6μJ to ~90ns/0.24μJ, bulk bitwise in-DRAM yields ~30–60× energy/perf gains, DB queries see 5–12×, and 3D near‑memory designs (e.g., 2,560 PUs) report ~13.8× graph speedups.

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" chapters (18)

1. 0:00Start
2. 2:21The Transformation Hierarchy of Computing
3. 8:08Memory Centric Computing
4. 10:05Personalizing Medicine
5. 15:31How Do We Handle Data
6. 16:13Design the System
7. 21:28Data Centric or Memory Centric Architectures
8. 24:14Technology Scaling
9. 52:52Energy Perspective
10. 1:01:30Data Copy Initialization
11. 1:13:54Programmable Issues
12. 1:14:11Sim Dram Framework
13. 1:17:02Security Functions
14. 1:28:27Processing near Memory
15. 1:30:25Graph Processing
16. 1:32:47Results
17. 1:34:16Simple Function Offloading
18. 1:36:18Quantization