Neural Network Accelerator Design
summary
Survey of >200 papers and 80 products compares CPUs, GPUs, FPGAs and ASICs and shows FPGA <1 TOPS/W vs ASICs pushing 10s–100s TOPS/W; quantization and pruning drive gains (quantization lets ~10× more MACs per area, pruning cuts ~90% of ops). GNNs present extreme sparsity (<1%) and GPUs run sparse aggregation ~30× slower than dense kernels, so the group builds DGSPARSE and a wrapper that yields ~10× system acceleration and 10× faster development. Also covers interruptible FPGA runtimes, cloud virtualization, and open-source AwesomeNAS for hardware-aware NAS.
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chapters (32)
- 0:00Introduction
- 1:00Artificial Neural Network
- 2:04Object Detection
- 6:46CPU Performance
- 7:36GPU Clusters
- 7:59Different Applications
- 8:25Data Growth
- 8:54Hardware
- 13:19Design Flow
- 18:58Loop Implementation
- 19:47Recurrent Neural Network
- 21:10Key Information
- 22:56Software Optimization
- 23:18Quantization
- 24:18Reduce Model Size
- 26:05Fast Convolution
- 27:06Loop Mapping
- 27:52Loop Interchange
- 32:01Onroad Design
- 33:22Onroad Parameters
- 35:21Architecture
- 38:08Design Automation
- 41:12Previous Work
- 41:57Optimization Opportunities
- 42:54Network Accelerator Comparison
- 43:30Findings
- 47:31Development
- 49:26Industry Trend
- 52:32Conclusions
- 52:57Summary
- 56:01Case Study
- 57:55Interrupt
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