A Case Study of Processing-in-Memory in off-the-Shelf Systems

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Evaluation of UPMEM PIM on a real server shows internal memory bandwidth and compute scale linearly with added DPUs, but practical limits appear: chip interleaving forces an SDK transpose that drops ~16 GB/s to ~13 GB/s per DDR channel, DPUs lack virtual memory and no DPU-to-DPU communication, and DPUs must be gang-scheduled at rank granularity (64 DPUs), causing batch processing. Experiments on Snappy, hyperdimensional computing, AES, JSON filtering and grep show superlinear Snappy speedups and small-data gains for hyperdimensional vectors, while AES stalls because AES-NI on CPUs outperforms DPUs for compute-bound work.

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" chapters (12)

1. 0:00Intro
2. 2:01PIM Models: Computation Outside Memory - Far
3. 2:53PIM Models: Computation Outside Memory - Near
4. 3:25Simulation vs Reality
5. 4:48UPMEM Architecture
6. 6:27Interleaving
7. 6:56Limitations
8. 9:18Evaluation
9. 9:57PIM performance compression
10. 10:30PIM performance: hyper-dimensional computing
11. 10:53PIM Capabilities: Encryption
12. 11:37Conclusion