Cortex-M(etal): Hyper-optimized Zephyr-Friendly Context Switching for a Mature Architecture
summary
Reworks the Cortex‑M context‑switch to a stack‑centric frame implemented as 17 thumb2 instructions (not yet Cortex‑M0 compatible), lands in a PR and shows a measurable win: 8% overall on target boards, with a tight microbenchmark ~70% faster on the core swap path. Uses ThreadMetric and deterministic QEMU to reproduce bugs (caught an FPU frame bit mistake), but the interrupt‑exit path costs ~18% due to swizzling; PendSV remains an available, higher‑latency alternative.
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chapters (15)
- 0:00Introduction
- 1:06Benchmark wake-up call
- 3:56Cortex-M architecture
- 8:13Thumb mode specifics
- 10:17PendSV challenges
- 13:06Legacy Zephyr switch
- 15:30Ideal stack frame
- 22:28Optimized assembly
- 28:04FPU alignment
- 31:10Interrupt exit fixup
- 36:26IT instruction interrupts
- 40:58FPU bug debugging
- 44:06Project lessons
- 47:35Performance results
- 50:24Call for review
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