Cortex-M(etal): Hyper-optimized Zephyr-Friendly Context Switching for a Mature Architecture
summary
A rewrite replaces the Cortex‑M PendSV heavy path with an inline, stack‑only context frame and a 17‑instruction resume sequence written in Thumb‑2 assembly, yielding about 8% speedup on real workloads and roughly 70% improvement in a tight microbenchmark. Tests, deterministic QEMU runs and hardware validate the approach, a lingering FPU-stack bug gets fixed, and the patch set lands as a pull request still needing review; interrupt‑exit swizzling remains slower and needs follow‑up but the core change compiles and runs.
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chapters (15)
- 0:00Introduction
- 1:06Benchmark wake-up call
- 3:56Cortex-M architecture
- 8:13Thumb mode specifics
- 10:17PendSV challenges
- 13:06Legacy Zephyr switch
- 15:30Ideal stack frame
- 22:28Optimized assembly
- 28:04FPU alignment
- 31:10Interrupt exit fixup
- 36:26IT instruction interrupts
- 40:58FPU bug debugging
- 44:06Project lessons
- 47:35Performance results
- 50:24Call for review
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