Direct Universal Access: Making Data Center Resources Available to FPGA
summary
DUA implements an FPGA-side IP layer plus a CPU control plane that uses server IPs as top-level names to give FPGAs global names and a unified socket-like interface, with per-server control agents and an overlay crossbar in the data plane. It routes without CPU involvement, bypasses CPU for forwarding, and keeps per-forward latency under ~200 ns (≈0.2 μs) and under 50 ns per hop, at about 10% logic overhead. Built examples: deep crossing latency down 50% and regex matching with half the latency and up to 3× throughput.
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chapters (16)
- 0:00Intro
- 0:21FPGA Deployment in Data Centers
- 0:38Resource Access Requirements
- 1:27Current FPGA Communication Architecture
- 2:49Programming Interface
- 3:42Accessibility
- 4:15Multiplexing
- 5:16Security
- 5:56Direct Universal Access
- 6:42DUA Overview
- 8:38System Architecture
- 9:19DUA Control Plane
- 12:41Evaluation - Logic Overhead
- 13:07Evaluation - Deep Crossing
- 14:15Evaluation - Regex Matching
- 14:59Conclusion
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