Concurrency Challenges of Interrupt Service Routines
summary
Shows that Interrupt Service Routines on Cortex-class MCUs inject execution by saving a few registers and jumping via the nested vector interrupt controller, so ordinary C++ code gets unexpected races (about 30% of volatile-marked variables are actually races). Disabling interrupts is a common but fragile fix; a safer approach is priority-based locking plus small CAS-backed queues. An implemented solution uses meta-programming to list resources and threads, auto-generate locking and a scheduler that proves no deadlock or starvation below a given priority, and it works in practice.
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chapters (14)
- 0:00Introduction and motivation
- 1:49Defining the problem
- 5:11Naive event-based implementation
- 10:46CPU state and program counter
- 18:09Latency and jitter explained
- 23:57Threads vs real-time constraints
- 31:03Interrupt Service Routines basics
- 33:13Race conditions in ISRs
- 35:24Disabling interrupts drawbacks
- 41:50Priority inversion and starvation
- 45:05Emil's starvation-free scheduler
- 50:50Language features and shared state
- 52:59Future of microcontroller C++
- 53:45Q&A session
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