Precise Data Center Traffic Engineering with Constrained Hardware Resources
Talkat 21st USENIX Symposium on Networked Systems Design and Implementation (NSDI '24) · 2024-04-16..04-18·
summary
System adapts switch memory allocation to flow volume and precision loss, prunes select ports and merges identical weight distributions to implement TE on constrained hardware. Two reduction algorithms are implemented: a mixed integer solver and a greedy search that apply group sharing, table carving, and table pruning to fit groups into limited entries. Evaluation on realistic traces shows TE is approximated within 7% error versus 67% for prior table fitting, avoids rule overflow, and runs about 10× faster.
AI-written summary · about
chapters (11)
- 0:00Introduction
- 2:04How TE works
- 3:47Limited switch memory
- 5:33Precision loss effects
- 7:43Root causes of precision loss
- 10:09Limitations of group reduction
- 11:52New heuristics for group reduction
- 12:14DMIR and IGR algorithms
- 13:58Evaluation: link utilization & flow completion
- 15:22Performance speed & comparison
- 16:29Summary
related talks
25mVirtualizing Traffic Shapers for Practical Resource Allocation
17mTraffic Engineering for AI Training Networks
17mDOTE: Rethinking (Predictive) WAN Traffic Engineering
16mSöze: One Network Telemetry Is All You Need for Per-flow Weighted Bandwidth Allocation...
22mAdapting TCP for Reconfigurable Datacenter Networks
21mSemi-Oblivious Traffic Engineering: The Road Not Taken
17mNetHint: White-Box Networking for Multi-Tenant Data Centers
16mPowerTCP: Pushing the Performance Limits of Datacenter Networks
