Finding NEMO: Nimble and Expressive Memory Observability
Talkat 20th USENIX Symposium on Operating Systems Design and Implementation (OSDI '26) · 2026-07-13..07-15·
summary
NEMO implements a programmable three‑stage telemetry pipeline in the memory controller and prototypes it on an FPGA-based CXL memory controller (Altera Agel 7 IE dev kit with 16 GB DDR), duplicating requests off the data path and keeping state in on‑MC SRAM. It speeds HeMem’s hot‑set recovery 5× faster, accelerates MEMTIS huge‑page splitting 10.4×, and detects noisy neighbors with 350× lower CPU overhead, yielding up to 1.7× throughput and 23% latency reduction.
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chapters (11)
- 0:00NEMO project intro
- 1:23Existing telemetry limits
- 3:51High-fidelity telemetry need
- 4:13NEMO co-design overview
- 5:36NEMO pipeline architecture
- 6:41Huge page access skewness
- 8:26Prototype overhead
- 9:09Hotset tracking with HEM
- 10:56Splitting hot huge pages
- 12:20Performance isolation across tenants
- 14:26Conclusion and release
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