TileLoom: Automatic Dataflow Planning for Tile-Based Languages on Spatial Dataflow Accel…
Talkat 20th USENIX Symposium on Operating Systems Design and Implementation (OSDI '26) · 2026-07-13..07-15·
summary
TileLoom is an MLIR-based end-to-end compiler that lowers tile-based DSLs (Halide and Triton) to spatial dataflow accelerators by mapping tile grids across a 2D core array, generating inter-core and intra-core schedules, and using a hardware DF dialect to model topology, memory, and compute. It compiles candidates, prunes infeasible mappings, and selects via a performance model; on two Tenstorrent generations it matches vendor TTN, gives ~2× speedup on flash attention and ~15–30× for fused member-chunk kernels, while losing ~20% on decode workloads.
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chapters (11)
- 0:00TileLoom introduction
- 1:22Memory wall and dataflow
- 5:18Tile-based DSL challenges
- 7:28TileLoom compilation
- 8:31Inter-core dataflow planning
- 12:05Hardware modeling with DF
- 13:51Intra-core scheduling
- 14:54Evaluation setup
- 15:37Tensor Core comparison
- 17:44Performance results
- 19:50Key takeaways
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