Generating Circuits with Generators
summary
YieldFSM is a generator-based HDL that represents clock-level timing so designers get higher-level code with explicit cycles; the compiler (using continuation-passing style and defunctionalization) targets Mealy machines and is implemented with Template Haskell and Clash. Examples include a full HD44780 initialization implemented in 149 lines and 26 timing blocks, and three RISC-V datapaths where control is replaced by FSM code that is much smaller; the designs functionally work but one case shows unexplained performance loss.
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chapters (7)
- 0:00Motivation
- 1:58Digital Secret
- 2:45Examples
- 4:51YieldFSM
- 9:07Compiler
- 11:26Applications
- 14:15Implementation
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