Porting the Oberon system to the RISC-V instruction set architecture
summary
Porting Oberon to RISC-V produces a working RV32IM system: the compiler and dynamic linker are rewritten, the build pipeline uses Project Nuribo and a modified microcore emulator, and the resulting self-compiling system draws a Sierpinski curve and recompiles itself. Work-RISCv’s floating point and interrupts turn out unused so the target reduces to 12 instructions; branch offsets (24→12 bits) force extra jumps. Binaries run slightly slower and are about 14% larger, but the port succeeds.
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chapters (10)
- 0:00Introduction
- 1:04Oberon and RISC-V overview
- 7:44Targeting RISC-V for Oberon
- 10:15Build pipeline setup
- 11:39Porting compiler challenges
- 15:30Linker and system porting
- 17:15Results and performance
- 17:59Live demonstration
- 18:42Lessons and value
- 20:48Q&A
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