Debugpci: Making PCIe Common Error Debugging Easier
Talkat Embedded Linux Conference @ Open Source Summit North America 2022 · on Friday, 2022-06-24· at 11:10· Room 203/204 (Level 2), JW Marriott Austin, 110 E 2nd Street Austin, TX 78701·
summary
Command line tool debugpci integrates into pciutils and reads DesignWare controller debug registers to capture lane‑wise counters and state snapshots then dump human‑readable reports with counts and one‑line root cause suggestions. It captures equalization phase results per lane, receiver detection timeouts, correctable/uncorrectable error counts (example fc protocol error count = 1), framing error details and rx_valid per lane, and recommends register changes like holding LTSSM or increasing EQ timeouts. It replaces manual bit twiddling and works on live systems without a hardware analyzer.
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chapters (14)
- 0:00Introduction
- 5:02Debug Features in DesignWare PCIe Controller
- 7:55Existing PCle Debugging Procedure
- 10:06Need for Streamlined PCle Debugging Procedure
- 12:00pciutils - Open Source Tool for Diagnosis
- 17:45Architecture And Software Stack of debugpci
- 20:20Software Implementation: Main Function
- 23:15Software Implementation: Capture Function
- 25:10Software Implementation: Dump Function
- 27:40Real Use-Cases
- 33:18Real Use-Case: Healthy PCle link
- 35:00Real Use-Case: Uncorrectable Errors
- 36:06Real Use-Case: Framing Error
- 37:38Real Use-Case: Broken Lanes
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