Reliable and Secure Embedded Systems
summary
Three concrete results: a DSS-modulated thermal covert channel multiplies a PN sequence into CPU heating to hide bits (simulator and real desktop tests show detection drops drastically), and a countermeasure using a differential filter plus targeted noise jamming recovers detection with optimum threshold ~0.03–0.035, <10 ms processing and ~14 W power overhead. An erDAC on Xilinx FPGA implements a UDP-based remote direct access controller, cutting latency 40–75%, CPU almost zero, energy ~0.25 mJ/Mb at 25 mW. A segment method using word-level CQCC + avg ZCR with a GMM reaches lowest EER/t-DCF vs nine baselines and the fastest embedded 92%‑accuracy response.
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chapters (18)
- 0:00Start
- 18:29Remote Access Controller
- 19:27Hardware architecture
- 19:54Command/Response Protocol
- 21:34Latency
- 22:27CPU consumption
- 22:45Resources utilization
- 28:00INTRODUCTION
- 29:28MOTIVATION
- 30:41SEGMENT-BASED FEATURE EXTRACTION
- 31:53BIASED DECISION STRATEGY
- 33:14EXPERIMENT EVALUATION
- 41:34Hardware Defects in DNN Accelerators
- 42:11Hardware Fault Isolation with Bypassing
- 44:11Minimizing DNN Accuracy Loss
- 45:58Bringing Hardware Parameters Into Loop
- 49:07PE Bypass Resilience (Weight-Stationary)
- 50:41Hardware Overhead Analysis
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