Using Customerized QEMU Co-simulation for Development and Test of Zephyr Applications
summary
Claims a working Cortex-M33 + Tensilica Xtensa co-sim built by customizing QEMU so unmodified Zephyr binaries boot and communicate. Implements a custom QEMU device: message unit mapped to real-SoC addresses, uses D-Bus + Python daemon for real‑time IPC between two QEMU processes, and demonstrates an IPM-based message round trip on an RT595-like board model. Uses the sample Xtensa controller (not full DSP silicon), supports CI/code‑coverage runs, and the code will be open‑sourced after license checks.
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chapters (9)
- 0:00Customized QEMU co-simulation intro
- 1:15Traditional SoC challenges
- 3:46What is QEMU
- 8:25Co-simulation for hybrid SoCs
- 13:53Message unit devices in QEMU
- 19:19Zephyr RTOS integration
- 22:17Zephyr-based SoC simulator
- 27:43Live simulator demo
- 30:32Benefits and future uses
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