AP Power Sequence Subsystem
summary
Describes an implemented Zephyr subsystem API that manages ACPI AP power states (G3, S5–S0) and runs on the Zephyr State Machine Framework, mapping each ACPI state into three hierarchy levels: architecture, chipset, application. Provides mandatory macros and APIs to register entry/run/exit handlers, post events, lock processing and receive notifications; enforces one transition per iteration and hierarchical entry/exit ordering. Warns that missing handlers or next-state entries block the state machine and that callbacks run in the driver thread, so careful locking is required.
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chapters (13)
- 0:00Introduction
- 0:47Chrome OS EC background
- 3:55AP power sequence explained
- 5:07Motivation for AP power sequence
- 6:11AP power sequence overview
- 9:22Zephyr state machine framework
- 12:38Hierarchical state machine
- 13:43Execution flow of AP power sequence
- 15:09Implementing AP power sequence
- 18:44State transition entry/exit
- 20:06Ultimate hook pattern
- 21:54User interface and services
- 23:40Summary
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