Wavefront Threading Enables Effective High-Level Synthesis
summary
Kagawa is a hardware language that maps wavefront threading directly to pipelines so the compiler does minimal work and performance is predictable; threads keep a fixed order and shared-memory accesses enforce that order. The team compiles one-thread-per-instruction simulators into hardware, runs a soft RISC-V pipeline on Altera FPGAs and reports competitive area/performance against Nios processors, and the IP is already deployed in Microsoft datacenter FPGAs. pipeline for and one thread per clock cycle describe key limits.
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chapters (18)
- 0:00Kagawa introduction
- 1:22Hardware description language challenges
- 2:26Shared memory threading
- 3:08Wavefront threading model
- 4:33Wavefront memory model
- 5:55Pipeline loops ordering
- 6:57Code to hardware mapping
- 7:39Control flow in loops
- 8:43Loop composition
- 9:46Predictable performance
- 10:27Horizontal library design
- 11:07Execution reasoning
- 11:49Atomicity scheduling
- 12:32Thread ordering sync
- 13:36Processor results
- 14:59FPGA deployment
- 15:39Open problems
- 17:24Q&A
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