Panel+Closing
summary
NOC energy, not latency, drives current designs because AI workloads demand massive parallelism with low‑precision (4–8 bit) compute and terabyte‑scale data, so minimizing bit‑movement wins. Examples: a 72‑core Grace chip links cores, caches and LPDDR for scalable coherence; wafer‑scale systems (84 dies) and 47‑tile GPUs show package‑level networking. Practical tools include a model compiler for automatic abstraction and queuing‑network transforms to produce fast analytical latency models for optimization and design space search. Photonics inside the die remains costlier and not yet energy‑competitive.
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chapters (11)
- 0:00Start
- 2:47Axel Jones
- 3:40Michael Kishinevsky
- 23:38Packaging and the 3d Integration
- 31:59Workload Models
- 35:42Automated Abstraction
- 38:15What Is Important in Academic and Interaction between Industry and Academia
- 43:45Wafer Scale Integration
- 45:53Education
- 1:12:06Disruptive Change in the Interconnect
- 1:12:37Barrier Synchronization
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