Keynote II

on YouTube ↗01h 05m

" summary

Claim: on-chip wires dominate energy and latency, so a 2D mesh (add diagonals if possible) plus separate request/reply networks wins. Router design uses simple direction-order routing and two‑phase request/ack flow control with no virtual channels, yielding about 100 ps input‑to‑output router delay and wire‑dominated nanosecond tile transit. Circuits reuse supply to cut wire energy ~4x in silicon prototypes taped into a GPU shuttle, and embedded AND‑tree barriers give 20–30 ns global syncs on large chips.

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" chapters (14)

1. 0:00Start
2. 10:10Network Design
3. 18:28Asynchronous Flow Control
4. 26:38Summarize the Router Design
5. 31:13The Elastic Buffer Flow Control
6. 38:27Crosstalk
7. 41:18Fast Barrier Network
8. 44:26Half Cycle Synchronizers
9. 45:47Future Directions
10. 48:50Optimum Repeater Delay
11. 49:23What Is the Maximum Achievable Signal Velocity for these 80 Nanometer Pitch Wires
12. 51:42Standardized Interfaces
13. 52:22Barriers to Entry
14. 55:47Low Energy Circuits To Drive the Wires