Trap-less Virtual Interrupt for KVM on RISC-V
summary
Proposal extends RISC-V interrupt controller (CLINT/PLIC) with new CSRs and implements KVM + QEMU emulation support to deliver trap-less delivery of virtual timer, software-generated and external supervisor interrupts directly to vCPUs. Implementation runs in QEMU/RISC-V emulator and KVM, uses Redis and UnixBench and ping for microbenchmarks, and measures ~60–70% speedup on timer paths, ~50% with vIPI plus 11% lower ping latency while cutting ~300k MMIO traps.
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chapters (16)
- 0:00Intro
- 0:30Trap-less Virtual Interrupt for KVM on RISC-V
- 1:14Background
- 4:14Motivation
- 5:54Virtualization-aware Core-Local Interrupt Controller (CLINT)
- 6:37Virtualization-aware PLIC
- 7:57Direct Injection of Virtual Interrupts
- 10:30KVM Support Overview
- 11:54Trap-less Virtual Interrupt - Timer Interrupt
- 12:53Trap-less Virtual Interrupt - Virtual Timer Interrupt
- 14:50Trap-less Virtual Interrupt - VSEI
- 21:33Implementation
- 22:17Benchmark Results - Virtual Timer Interrupts
- 22:52Benchmark Results - Timer & VSSI
- 23:19Benchmark Results - VSEI
- 24:27Future Work
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