HA-IOV: Applying Hardware-assisted Techniques to IO Virtualization Framework
summary
HA-IOV implements a RISC-V prototype that bypasses guest→QEMU roundtrips by adding user-level exception redirection, a virtual interrupt (VI) mechanism and hardware-assisted context switch (HCS). Changes include new CSRs and PTE bits to delegate traps and second-stage page faults to host user space, memory sharing between guest and host, and an interrupt controller mapping VR request→VID per CPU. Results: UART throughput ~2×, virtio-net (rehearsal/virtio) TCP/UDP >100% faster on small messages, and about 20% average I/O improvement in filebench waterblock, with higher CPU utilization from freed polling cores.
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chapters (9)
- 0:00Intro
- 0:52Background • High-performance computing in data centers ► 10 virtualization is one of the most crucial components to optimize physical resource
- 3:31Motivation - Paravirtual 1/0 Devices
- 6:11Overview of HA-IOV Architecture
- 9:05Implementation Prerequisite Privilege Mode In RISC-V Architecture
- 10:55HA-IOV for Emulated Virtual 1/0 Devices
- 17:21HA-IOV for Paravirtual 1/0 Devices in Kernel
- 20:50HA-IOV for Paravirtual 1/0 Devices in Userspace
- 28:13Conclusion and Future Work
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